System and method for reducing power consumption in waiting mode

ABSTRACT

A timer for measuring a time period including a high frequency generating unit, a low frequency generating unit and a controller connected to the high and low frequency generating units, wherein the controller deactivates the high frequency generating unit during at least a portion of the time period, detects and counts predetermined portions of the signals provided by the high and low frequency generating units and counts a plurality of the portions of the currently active frequency generating unit.

CROSS-REFERENCE TO PREVIOUS APPLICATIONS

[0001] This application is a continuation-in-part of U.S. Ser. No.08/906,089 filed Aug. 5, 1997.

FIELD OF THE INVENTION

[0002] The present invention relates to a method and system for lowpower precision timing, in general and to a method and a device forproviding improved power consumption, while maintaining precise timing,of a communication system in waiting mode, in particular.

BACKGROUND OF THE INVENTION

[0003] Methods and devices for providing precise timing and precise timecounting are known in the art. Such devices conventionally include acrystal for providing a basic frequency and a controller foraccumulating the clock signals generated by the crystal. When such asystem attempts to increase the accuracy of the counting mechanism, itutilizes a high frequency crystal which increases the resolution intime.

[0004] It would be appreciated that frequency and energy are associatedin a way that producing a higher frequency requires higher power to beprovided thereto. The basic quantum rule is presented by the expression:

E=h·f

[0005] wherein E represents energy, h represents Plank's coefficient andf represents frequency.

[0006] In CMOS design, the following expression is used:

P=C·V ² ·f

[0007] wherein P represents power, C represents capacity and Vrepresents voltage.

[0008] Methods for managing power of a communication system in waitingmode are known in the art. A conventional communication system, inwaiting mode has to detect hailing signals and open a communicationchannel when it detects a hailing signal which is addressed thereto.

[0009] Conventional communication protocols, such as TDMA, determinetime periods in which hailing signals are transmitted. State of the artcommunication systems, attempt to shut down their receiver, when out ofthese time periods, so as to save power. Such systems are described inU.S. Pat. No. 5,568,513 to Thomas et al and U.S. Pat. No. 5,224,152 toHarte.

SUMMARY OF THE PRESENT INVENTION

[0010] It is an object of the present invention to provide a novelmethod and device for reducing power consumption of a communication unitin waiting mode.

[0011] It is a further object of the present invention to provide anovel method and system for low powered timing.

[0012] According to the present invention there is thus provided a timerfor measuring a time period including a high frequency generating unit,a low frequency generating unit and a controller connected to the highand low frequency generating units. The controller deactivates the highfrequency generating unit during at least a portion of the time period.The controller further detects and counts predetermined portions of thesignals provided by the high and low frequency generating units.Furthermore, the controller counts a plurality of the portions of thecurrently active frequency generating unit.

[0013] The timer can also include means, connected to the controller,for estimating the frequency of the low frequency generating unit.

[0014] According to another aspect of the present invention, there isprovided a method for providing an indication of a time period T whichcommences at time t₁ and expires at time t₂ the method including thesteps of:

[0015] activating a high timing level at time t₁;

[0016] counting a first predetermined number M of predetermined cycleportions of the high timing level for determining a first partial timeperiod;

[0017] activating a low timing level at the end of the first partialtime period; and

[0018] counting a second predetermined number N of predetermined cycleportions of the low timing level.

[0019] According to the invention, the method can further include a stepof indicating the expiration of the time period at time t₂.

[0020] For example, the first predetermined number M and the secondpredetermined number N satisfy the following equation:

T=N×T _(L) +M×T _(H)

[0021] wherein T_(H) represents a time period determined by thepredetermined cycle portions of the high timing level and T_(L)represents a time period determined by the predetermined cycle portionsof the low timing level.

[0022] The method of the invention, can further include a step ofdeactivating the high timing level after the step of activating the lowtiming level.

[0023] The method can further include a step of calculating the positionof a synchronization signal every predetermined synchronization timeperiod. This time period can be determined according to the time periodof a repetitive synchronization sequence. For example, in thecommunication standard IS-95 this time period is approximately 26.6milliseconds.

[0024] To enhance accuracy, the method of the present invention, canfurther include a step of estimating the frequency of the low timinglevel.

[0025] According to a further aspect of the present invention, there isprovided a communication system which includes a receiver, and a timerfor measuring a time period. The timer includes a high frequencygenerating unit, a low frequency generating unit and a controllerconnected to the high and low frequency generating units. The controlleris further connected to the receiver.

[0026] The controller deactivates the high frequency generating unitduring at least a portion of the time period, deactivates the receiverduring at least another portion of the time period, detects and countspredetermined portions of the signals provided by the high and lowfrequency generating units and counts a plurality of the portions of thecurrently active frequency generating unit.

[0027] The communication system of the invention, can further includemeans, connected to the controller and to the receiver, for estimatingthe frequency of the low frequency generating unit.

BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The present invention will be understood and appreciated morefully from the following detailed description taken in conjunction withthe drawings in which:

[0029]FIG. 1 is a schematic illustration of a timing diagram of twotiming levels, in accordance with a preferred embodiment of the presentinvention;

[0030]FIG. 2 is a schematic illustration of a method for providing atime count of a predetermined time period T using the two timing levelsof FIG. 1, in accordance with a further preferred embodiment of thepresent invention;

[0031]FIG. 3 is a schematic illustration of a timing diagram of twotiming levels, in accordance with another preferred embodiment of thepresent invention;

[0032]FIG. 4 is a schematic illustration of a method for providing atime count of a predetermined time period T using the two timing levelsof FIG. 3, in accordance with another preferred embodiment of thepresent invention;

[0033]FIG. 5 is a schematic illustration of a timing diagram of twotiming levels, in accordance with yet another preferred embodiment ofthe present invention;

[0034]FIG. 6 is a schematic illustration of a timing system, constructedand operative in accordance with another preferred embodiment of thepresent invention;

[0035]FIG. 7 is a schematic illustration of a method for operating thesystem of FIG. 6, providing a time count of a predetermined time periodT using the two timing levels of FIG. 5, operative in accordance withanother preferred embodiment of the present invention; and

[0036]FIG. 8 is a schematic illustration of a timing system, constructedand operative in accordance with a further preferred embodiment of thepresent invention;

[0037]FIG. 9 is a schematic illustration of a method, operative inaccordance with another preferred embodiment of the present invention;and

[0038]FIG. 10 is a schematic illustration of a timing scheme, accordingto the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0039] The present invention overcomes the disadvantages of the priorart by providing a timing mechanism which includes two levels of timing.

[0040] A high timing level, which provides high resolution timing and alow timing level which provides low timing resolution, combined with alow power consumption. The combination of these two timing levels,according to the invention, reduces power consumption significantly.

[0041] Reference is now made to FIG. 1, which is a schematicillustration of a timing diagram of two timing levels, in accordancewith a preferred embodiment of the present invention.

[0042] Time period 10, from t₁ to t₃, represents a predetermined timeperiod which needs to be counted and indicated. Timing level 12 is ahigh frequency timing level. Timing level 14 is a precise low frequencytiming level. Maintaining timing level 12 requires more power thanmaintaining timing level 14.

[0043] Time period 10 can not be represented by a natural number of halfcycles of the low timing level 14. When t₁ is aligned with the risingpoint of the first cycle of the low timing level 14 then, t₃ occurswithin the last cycle 16 of low timing level 14.

[0044] t₃ does not align with either a rise or a fall of a cycle of thelow timing level 14. Thus, the low timing level 14 can not be used toindicate t₃. It will be appreciated that time period 10 can berepresented by the expression:

T=N×T _(L) +M×T _(H) +ε; ε<T _(H)

[0045] wherein T represents time period 10, T_(H) represents half of asingle cycle of the high timing level, T_(L) represents half of a singlecycle of the low timing level and M and N are natural numbers.

[0046] It will be appreciated that a conventional oscillators and forthat matter, crystal, incorporates and error. Accordingly, the T_(H) andT_(L) have errors ΔT_(H) and ΔT_(L), respectively. Thus, N and M areevaluated according to these errors so that

|T−(N×T _(L) +M×T _(H))|≦ΔT

[0047] wherein ΔT is a maximal predetermined error of time period T.

[0048] t₂ represents a point in time where the last rise or fall of thelow timing level 14, which occurs before t₃. At t₂, the high timinglevel 12 is activated and the low timing level 14 is deactivated. Then,the high timing level 12 counts the time period from t₂ to t₃ andprovides an indication of t₃.

[0049] Accordingly, the present invention provides high resolutiontiming mechanism, using a combination low timing level and high timinglevel, wherein the overall resolution is determined according to theresolution of the high timing level.

[0050] Reference is now made to FIG. 2, which is a schematicillustration of a method for providing a time count of a predeterminedtime period T using the two timing levels of FIG. 1, in accordance witha further preferred embodiment of the present invention.

[0051] In step 20, the low timing 14 is activated at the beginning oftime period T.

[0052] In step 22, N half cycles of the low timing level are counted,wherein $N = {{{int}\left( \frac{T}{T_{L}} \right)}.}$

[0053] Right after these N half cycles, the high timing level 12 isactivated and the low timing level 14 is deactivated (step 24)

[0054] In step 26, M half cycles of the high timing level are counted,wherein$M = {\frac{{{frac}\left( \frac{T}{T_{L}} \right)} \cdot T_{L}}{T_{H}}.}$

[0055] It will be noted that a compatible calculation using an integerfunction is also applicable for this step.

[0056] In step 28, the end of time period T is indicated.

[0057] Reference is now made to FIG. 3, which is a schematicillustration of a timing diagram of two timing levels, in accordancewith another preferred embodiment of the present invention.

[0058] Time period 30, from t₁ to t₃, represents a predetermined timeperiod which needs to be counted and indicated. Timing level 32 is ahigh frequency timing level. Timing level 34 is a precise low frequencytiming level. Maintaining timing level 32 requires more power thanmaintaining timing level 34.

[0059] Time period 30 can not be represented by a natural number of halfcycles of the low timing level 34. When t₃ is aligned with the risingpoint of the first cycle of the high timing level 32 then, t₁ occurswithin a cycle 36 of low timing level 34. t₁ does not align with eithera rise or a fall of a cycle of the low timing level 34. Thus, the lowtiming level 34 can not be used to indicate t₃.

[0060] t₂ represents a point in time where the first rise or fall of thelow timing level 34, which occurs right after t₁. The time period fromt₂ to t₃ can be represented by a natural number of half cycles of thelow timing level 34.

[0061] At t₂, the low timing level 34 is activated and the high timinglevel 32 is deactivated. Then, the low timing level 34 counts the timeperiod from t₂ to t₃ and provides an indication of t₃.

[0062] Reference is now made to FIG. 4, which is a schematicillustration of a method for providing a time count of a predeterminedtime period T using the two timing levels of FIG. 3, in accordance withanother preferred embodiment of the present invention.

[0063] In step 50, the high timing level 34 is activated at thebeginning of time period T.

[0064] In step 52, M half cycles of the high timing level are counted,wherein$M = {\frac{{{frac}\left( \frac{T}{T_{L}} \right)} \cdot T_{L}}{T_{H}}.}$

[0065] Right after these M half cycles, the low timing level 34 isactivated and the high timing level 32 is deactivated (step 54)

[0066] In step 56, N half cycles of the low timing level are counted,wherein $N = {{{int}\left( \frac{T}{T_{L}} \right)}.}$

[0067] In step 28, the end of time period T is indicated.

[0068] Some oscillators, after they are activated, require at least apredetermined period of time to stabilize, before they can produceconstant stable frequency signal. Accordingly, the present inventionprovides a solution which enables utilizing such oscillators.

[0069] Reference is now made to FIG. 5, which is a schematicillustration of a timing diagram of two timing levels, in accordancewith a further preferred embodiment of the present invention.

[0070] Time period 100, from t₁ to t₆, represents a predetermined timeperiod which needs to be counted and indicated. Timing level 102 is ahigh frequency timing level. Timing level 104 is a precise low frequencytiming level. Maintaining timing level 102 requires more power thanmaintaining timing level 104.

[0071] According to the invention, once t₁ is detected, using hightiming level 102, then, the low timing level 104 is activated. t₂represents a point in time where the high timing level 102 and the lowtiming level 104 align, after which the high timing level 102 can bedeactivated. Accordingly, the high timing level 102 is deactivated attime point t₃. The time period from t₁ to t₂ is represented by M₁ halfcycles of the high timing level.

[0072] According to the present example, t₆ occurs within a cycle of thelow timing level 104. Accordingly, the low timing level 104 can notindicate t₆ with sufficient accuracy.

[0073] Low timing level 104 counts a time period from t₂ to t₄, at lowpower consumption. At t₄, after the low timing level 104 has counted apredetermined number of half cycles N, then, the high timing level 102is reactivated. It will be appreciated by those skilled in the art thatconventionally, when a crystal oscillator is activated, it requires sometime to stabilize thereby producing a constant frequency, as required.

[0074] t₅ represents a point in time in which the high timing level 102and the low timing level align. The low timing level 104 can bedeactivated after t₅.

[0075] Then, the high timing level 102 counts M₂ half cycles, afterwhich, the end of time period 100 can be indicated.

[0076] Time period 10 can be represented by the expression:

T=N×T _(L)+(M ₁ +M ₂)×T _(H)

[0077] wherein T represents time period 10, T_(H) represents half of asingle cycle of the high timing level, T_(L) represents half of a singlecycle of the low timing level and M₁, M₂ and N are natural numbers.

[0078] Reference is made now to FIG. 6 which is a schematic illustrationof a timing system, generally referenced 200, constructed and operativein accordance with another preferred embodiment of the presentinvention.

[0079] System 200 includes a fast clock 202, for producing a highfrequency, a slow clock 204, for producing a low frequency and acontroller 206, connected to the fast clock 202 and the slow clock 204.

[0080] The controller 206 controls each of the clocks 202 and 204 so asto activate, deactivate, count and moderate them. The controller 206 isalso connected to a receiver 208. The controller 206 provides thereceiver timing frequencies. In the present example, the controller 206is also capable of activating, deactivating, enabling and disabling thereceiver 208.

[0081] Reference is also made to FIG. 7, which is a schematicillustration of a method for operating the system 200 of FIG. 6,providing a time count of a predetermined time period T using the twotiming levels of FIG. 5, in accordance with another preferred embodimentof the present invention.

[0082] In step 150, a high timing level 102 (FIG. 5) is maintained atthe beginning (t₁) of time period T (time period 100). Then, thecontroller 206 counts half cycles of the signal provided by the fastclock 202, from t₁ (step 152).

[0083] In step 154, a low timing level 104 (FIG. 5) is activated. In thepresent example, the controller 206 activates the slow clock 204 anddetects when the signals, provided by the slow clock 204 and the fastclock 202, align (step 156). In the present example t₂ of FIG. 5represents this alignment point. Then, the system 200 stops counting thesignal of the fast clock and starts counting the signal of the slowclock.

[0084] In step 158, the system 200 stores the number of counts of thefast clock, from t₁ to t₂, in a variable M₁.

[0085] In step 160, the high timing level, represented by the fast clock202, is deactivated. In the present example, the controller 206 shutsdown the fast clock 206 at t₃. It will be noted that when the powerconsumption of system 200 is considerably lower when the slow clock 204is operative then power consumption achieved when the fast clock 202 isoperative. It will be further appreciated that when the controller 206is connected to an external device, such as receiver 208, then, thecontroller 206 may disable this device or shut it down, for furtherpower consumption decrease.

[0086] In step 162, the N half cycles of the low timing level, arecounted. In the present example, the controller 206 counts N half cyclesof the signal provided by the slow clock 204, according to theexpression:$N = {{{int}\left( \frac{T - {M_{1} \times T_{H}}}{T_{L}} \right)}.}$

[0087] In step 164, the high timing level 106 is reactivated atT_(STABILIZE), which is a point in time before N half cycles of the lowtiming level are completed, required for stabilizing the high timinglevel. In the present example, the controller 206 reactivates the fastclock 202 at t₄.

[0088] In step 166, a point in time is detected, where the high timinglevel 102 and the low timing level 104 align. It will be noted that thispoint in time should also represent the completion of counting N halfcycles of the low timing level. In the present example, the controller206 detects when the fast clock 202 and the slow clock 204 align (t₄).

[0089] In step 168, M₂ half cycles of the high timing level 102 arecounted. In the present example, the controller 206 counts the halfcycles of the signal provided by the fast clock 202 according to theexpression:$M_{2} = {\frac{{{frac}\left( \frac{T - {M_{1} \times T_{H}}}{T_{L}} \right)} \cdot T_{L}}{T_{H}}.}$

[0090] In step 170, after completing the count of M₂ high timing levelhalf cycles, the end of the time period T is indicated. In the presentexample, the controller 206 indicates the end of time period 100 to thereceiver 208.

[0091] For example, in a cellular TDMA implementation, the slow clock204 comprises a clock of up to 100 KHz and the fast clock 202 comprisesa clock of up to 20 MHz. Such clocks are manufactured and sold byDAISHINKU CORP., a Japanese company which is located in Tokyo andVectron, a US company, which is located in New-York. It will be notedthat any oscillating mechanism is applicable for the present invention.

[0092] In TDMA, a hailing signal lasts for about 50 ms and may bedetected once every 1 second. A conventional timer would use fastcrystal, thereby requiring energy E_(OLD) which is given by thefollowing expression:

E _(OLD) =P _(OLD) ·T=C·V ²·2·10⁷·1 sec

[0093] A timer constructed according to the present invention, use fastcrystal (for example at a frequency of 20 MHz) and a slow crystal (forexample at a frequency of 100 KHZ) combination, thereby requiring energyE_(NEW) which is given by the following expression:

E _(NEW) =P _(NEW) ·T=C·V ²·(2·10⁷·0.005 sec+1·10⁵·0.95 sec)

[0094] Accordingly, the ratio $\frac{E_{NEW}}{E_{OLD}} < {6\%}$

[0095] defines that using a timer constructed and operative, inaccordance with the present invention, would decrease the powerconsumption of a cellular unit, in wait mode, by at least ninety-fourpercent.

[0096] Low frequency crystals are generally susceptible to frequencyshifts due to environmental changes with respect to temperature,humidity and the like. In communication implementation of the invention,which will be discussed hereinbelow, the frequency of the low timinglevel has to be evaluated from time to time.

[0097] Accordingly, the receiver 208 provides an indication of thefrequency of a received signal, which was originally sent by areferenced station. In cellular communication, such a reference stationcan be a cellular base station which conventionally comprises a highprecision high frequency timing crystal, incorporated in a precise andstable frequency mechanism.

[0098] The controller 206 utilizes the reference frequency, provided bythe receiver 208, to evaluate the frequency of the low timing level.This process is performed, thoroughly, before the system 200 enterswaiting mode and constantly, during this waiting mode, each time thatthe receiver 208 is activated.

[0099] Since, a typical duty cycle of the system takes no more thanseveral seconds, the controller 206 is able to evaluate the frequency ofthe slow clock 204, with enhanced accuracy.

[0100] Reference is made now to FIG. 8 which is a schematic illustrationof a timing system, generally referenced 300, constructed and operativein accordance with a further preferred embodiment of the presentinvention.

[0101] System 300 includes a fast clock 302, a slow clock 304 and atiming controller 306 which is connected to the fast clock 302 and theslow clock 304. The timing controller 306 includes a processor 318, twocounters 314 and 316, which are connected to the processor 318 and anestimator 310, which is connected to the processor 318.

[0102] The counter 314 counts portions of the signal provided by thefast clock 302 and is connected thereto. The counter 316 counts portionsof the signal provided by the slow clock 304 and is connected thereto.

[0103] The estimator 310 is further connected to clocks 302 and 304 andto a receiver 308. The processor 318 is also connected to the receiver308 and controls it. The receiver 308 receives signals from and antenna312.

[0104] According to the present example, system 300 controls receiver308, thereby activating, deactivating and supplying it with operatingfrequency. Furthermore, the system 300 performs timely estimations ofthe frequencies provided by clocks 302 and 304.

[0105] At first, the processor 318 activates the receiver 308. Thereceiver 308 receives an incoming reference signal from the antenna 312and provides it to the estimator 310. This signal includes a basefrequency which is considerably accurate. The reference signal alsoincludes synchronization data.

[0106] The estimator 310 further receives signals from the clocks 302and 304. Then, the estimator 310 provides frequency estimations to theprocessor 318 with respect to the frequencies generates by clocks 302and 304.

[0107] The processor 318 calculates values M and N, according to theestimations provided thereto. After the receiver 308 finished receivingthe reference signal, the processor 318 employs wait mode therebydeactivating the receiver 308 for a predetermined waiting time period T.

[0108] Then, the processor 318 operates the fast clock 302 and the slowclock 304, so as to measure this predetermined waiting time period T,according to any of the methods described hereinabove.

[0109] After the processor 308 indicated the end of time period T, itreactivates the receiver 308, which in turn receives a short hailingsequence in the above reference frequency. This hailing sequence oftenincludes a synchronization sequence.

[0110] According to the present invention, the receiver 308 may providean indication of the frequency of the reference signal or the signalitself, to the estimator 310, which in turn, utilizes it to re-estimatethe frequencies of the clocks 302 and 304 and provides their estimationsto the processor 318.

[0111] The receiver 308 further provides the synchronization sequence tothe processor 318. Then, the processor 318 utilizes the informationreceived from the receiver 308 and the estimator 310 to reassess M andN.

[0112] Finally, if the hailing signal did not include an indication ofthe identity of the receiver 308, then the receiver provides a commandto the processor 318, so as to re-enter wait mode.

[0113] It will be appreciated that the method of the present inventionis applicable to any communication system such as a cellular telephone,a pager, a wireless telephone. In addition, the present invention isalso applicable to any device which may require a low power highresolution timer such as computers, calculators, alarm detectors and thelike.

[0114] The following example demonstrates an implementation of thepresent invention for CDMA communication standards IS-95 and IS-98.

[0115] In CDMA, the short PN sequence (SPN) is a PN sequence, having alength of 2¹⁵, which is generated by a modified fifteen bit linearfeedback shift register. This sequence is the main spreading componentof the transmitted spread spectrum signal, with respect to the down-linkdirection.

[0116] The pilot signal is generally a predetermined PN sequence whichis transmitted by all of the base stations. Since each base station usesa unique offset of the PN sequence, then each mobile can synchronize toa selected base station by detecting the predetermined PN sequence, atthe unique offset of that base station. It will be noted that among theplurality of signals, which are transmitted by a base station, the pilotsignal channel is the most powerful one.

[0117] The long code is basically a PN sequence having a length of2⁴²−1, which is used, in the down-link direction (i.e. from the basestation to the mobile) for encryption and scrambling purposes. Each ofthese transmitted CDMA symbol is multiplied by a decimated long codebit, before transmission.

[0118] CDMA uses a group of orthogonal sequences, also known as Walshsequences, to distinguish the signals which are transmitted to variousmobile units. Accordingly, each mobile unit can detect a signal which isdestined for it, by multiplying the received signal by the Walshsequence, temporarily assigned thereto.

[0119] These CDMA standards enable dual mode operation of a mobile unitboth as a telephone (mode-T) and as a pager (mode pager).

[0120] When operating in mode-T, in waiting mode, the time periodbetween two subsequent hailing messages can be set to predeterminedvalues, between 1.28 and 5.12 seconds. When operating in mode-pager, thetime period between two subsequent hailing messages can reach a maximumof 163.8 seconds. The method according to the present inventionaddresses both modes, in a combined manner.

[0121] These CDMA standards impose strict frequency accuracyrequirements, which most oscillators do not meet. Accordingly, thereceiver has to compensate for any inaccuracy and error which are causedby the oscillators.

[0122] In conventional sleep modes, the voltage controlled temperaturecompensated crystal oscillator (VCTCXO) is running, thus enabling thereceiver to keep track of time (keeping a continuous count of Long code,SPN and the like). It will be noted that in a receiver which includes aVCTCXO and a chip set, the power consumption of the chip set in waitingmode is (I_(VCTCXO)+C·V·Z·M)·V, wherein Z denotes the number fast clockcounts in a single slow clock count.

[0123] The method of the present invention shuts down the VCTCXO, duringsleep mode and so, the time managing hardware unit runs according to aslow clock and is able to recover from the sleep mode and receive thepaging channel. The recovery stage puts the system in a position inwhich it would be, had it not gone into sleep mode.

[0124] CDMA IS-95 traffic and paging channels operate according to 20 msframes. The SPN sequence repeats every 26.6 ms. According to the presentinvention, the sleep mode mechanism operates according to time units(frames) of 26.6 ms. Inventors have found that operating the sleep modemechanism according to the SPN sequence time period, yields enhancedefficiency, since it “freezes” the SPN. It will be noted that thepresent invention can be implemented using a sleep mechanism, whichoperates according to any time period.

[0125] The prior art methods, disable selected units of the chip set forthe entire sleep period and hence, are able to recover only when thistime period has elapsed. This poses a disadvantage, when the user entersa waking-up command, before the end of the sleep time period.

[0126] According to the present invention, the sleep mode mechanismperforms a calculation of the current state, at the end of each timeunit (26.6 ms frame). Hence, the sleep mode mechanism, is able toprocess a waking-up command, received from the user, at any stage of thesleep time period.

[0127] Reference is now made to FIG. 9, which is a schematicillustration of a method, operative in accordance with another preferredembodiment of the present invention.

[0128] In step 400, the receiver estimates the frequency of the slowclock with reference to the frequency of the fast clock, during anoperation of paging reception.

[0129] In step 402, the receiver disabled the activity of most of thechip units in the chip-set, thereby entering sleep mode. The onlyhardware that remains active is responsible for counting the slow clockand compensating for drifts thereof.

[0130] In step 404, the receiver activates the slow clock counter andcomparator which are responsible for waking up the disabled chip unitsof the chip-set at the next receiving slot.

[0131] In step 406, the receiver stops all of the time managing hardwareunits at a selected point in time, at which the receiver is at a certainstate.

[0132] In step 408, the receiver advances the sleep mode timingmechanism. The slow clock counts estimated 26.6 ms frames. After eachsuch estimated frame, the sleep mode mechanism advances the system 26.6frame counter by one and at the same time, re-adjusts the long codestate by 32768 steps (i.e. which are the number of long code steps in a26.6 ms frame)

[0133] In step 410, the sleep mode mechanism compensates for any driftof the slow clock during sleep mode time. The drift is calculated asfollows:

T=N×T _(L) +M×T _(H)

[0134] Each time unit (26.6 ms) is represented by X×(slow clockcounts)+Y×(fast clock counts). Z denotes the number fast clock counts ina single slow clock count. W accumulates the number of additional fastclock counts during the sleep period. For every count of X slow clockcounts, the sleep time mechanism performs the following operations:

[0135] the sleep time mechanism accumulates additional Y counts into W.

[0136] When W is equal or greater then Z, then the following count oftime units (26.6 ms) will be performed according to X+1 slow clockcounts instead of X slow clock counts and the sleep mode mechanismdecreases W by Z counts.

[0137] In step 412, the sleep mode mechanism operates according to awaking up command. This command can either be generated internally bythe sleep mode mechanism, at the end of a predetermined time unit (26.6frame), which indicates that the sleep mode time-period has elapsed orit can be provided from the host.

[0138] At this stage the sleep mode mechanism, enables the VCTCXO, andafter the VCTCXO is stable, the sleep mode mechanism enables some of thedisabled units of the chip-set. It is noted that the sleep modemechanism awakes the VCTCXO a few cycles sooner, so that it will haveenough time to stabilize.

[0139] In step 414, the sleep mode mechanism sets the time managinghardware unit to a new position, as will be explained in further detailherein below. It will be noted that at this step, the sleep modemechanism reverts from slow clock time resolution to fast clock timeresolution and compensates according to the remaining W accumulated fastcounts.

[0140] In step 416, the sleep mode mechanism enables [re-activates] theremaining disabled chip units.

[0141] In step 418, the receiver uses a searching module for finaltuning the position of the time managing HW units and is thus ready toreceive the paging channel.

[0142] Reference is now made to FIG. 10, which is a schematicillustration of a timing scheme, according to the present invention.

[0143]FIG. 10 presents the timing signals of the chip-set fast clock440, the DSP clock 442 and the VCTCXO 444, which are all shut down atthe same time, in the beginning of the sleep mode time period.

[0144] In the last frame 450, the VCTCXO is enabled before the DSP clockand the chip clock, a predefined time before it is needed for runningthe DSP. It will be noted that this is done because the VCTCXO requirestime to stabilize.

[0145] The VCTCXO is then used by the HW to compensate for the remainingfast clock cycles, before reactivating the time managing HW unit in theregular operation mode.

[0146] It will be noted that the slow clock accuracy is very low, withcomparison to the 813 ns (which is the value of T_(C)) requirement ofthe communication standards. The accuracy of the slow clock is thusmeasured & estimated when ever the fast clock is active and accurate(CDMA receiving).

[0147] As explained herein above, operating the slow clock in sleep moderequires some parameters, which are measured, calculated, estimated andstored before entering sleep mode. The measurement and estimation ofthese parameters can be performed in many ways.

[0148] These parameters include the number of slow clock counts in atime unit (26.6 ms frame), the number of additional fast clock counts ina time unit (26.6 ms frame), the number of fast clock counts in a singleslow clock count, and the like.

[0149] It will be appreciated by persons skilled in the art that thepresent invention is not limited to what has been particularly shown anddescribed hereinabove. Rather the scope of the present invention isdefined only by the claims which follow.

1. A timer for measuring a timing period comprising: a high frequencygenerating unit; a low frequency generating unit; and a controllerconnected to said high frequency generating unit and to said lowfrequency generating units, wherein said controller deactivates saidhigh frequency generating unit during at least a portion of said timeperiod, wherein said controller further detects and counts predeterminedsignal portions of the signals provided by said high frequencygenerating unit and said low frequency generating unit.
 2. The timeraccording to claim 1 further comprising means, connected to saidcontroller, for estimating the frequency of said low frequencygenerating unit.
 3. A method for providing an indication of a timeperiod T which commences at time t₁ and expires at time t₂, the methodcomprising the steps of: activating a high timing level at time t₁;counting a first predetermined number M of predetermined cycle portionsof said high timing level for determining a first partial time period;and activating a low timing level at the end of said first partial timeperiod; counting a second predetermined number N of predetermined cycleportions of said low timing level.
 4. The method according to claim 3further comprising the step of indicating the expiration of said timeperiod at time t₂.
 5. The method according to claim 3 wherein said firstpredetermined number M and said second predetermined number N satisfythe following equation: T=N×T _(L) +M×T _(H) wherein T_(H) represents atime period determined by said predetermined cycle portions of said hightiming level and T_(L) represents a time period determined by saidpredetermined cycle portions of said low timing level.
 6. The methodaccording to claim 3 further comprising the step of deactivating saidhigh timing level after said step of activating said low timing level.7. The method according to claim 3 further comprising the step ofcalculating the position of a synchronization signal every predeterminedsynchronization time period.
 8. The method according to claim 7 whereinsaid predetermined synchronization time period is approximately 26.6milliseconds.
 9. The method according to claim 7 wherein saidpredetermined synchronization time period is determined according to thetime period of a repetitive synchronization sequence.
 10. The methodaccording to claim 3 , further comprising the step of estimating thefrequency of said low timing level.
 11. A communication systemcomprising: a receiver; and a timer for measuring a time periodcomprising: a high frequency generating unit; a low frequency generatingunit; and a controller connected to said high frequency generating unitand to said low frequency generating unit, wherein said controller isfurther connected to said receiver, wherein said controller deactivatessaid high frequency generating unit during at least a portion of saidtime period, wherein said controller deactivates said receiver during atleast another portion of said time period, wherein said controllerfurther detects and counts predetermined portions of the signalsprovided by said high frequency generating unit and said low frequencygenerating unit.
 12. The communication system according to claim 11further comprising means, connected to said controller and to saidreceiver, for estimating the frequency of said low frequency generatingunit.